The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
Previously, the semiconductor industry utilized various methods and structures to form high performance bipolar transistors. To achieve higher performance, it was important to minimize the size of the base contact in order to reduce parasitic capacitances. Additionally, it was desirable to be able to shrink the size of the transistors using photolithographic scaling techniques. Prior methods of forming high performance bipolar transistors typically relied on slot etching techniques which generally were difficult to control and costly from a manufacturing standpoint. One example of such a bipolar transistor is disclosed in U.S. patent publication number 2005/0012180 by inventor Freeman et al which was published on Jan. 20, 2005. The method used to form the high performance bipolar transistor etched narrow slots through a dielectric and used the narrow slots as a mask to form other portions of the transistor. These prior bipolar transistor structures also used multiple oxide or photoresist plugs to alternatively define both outside and inside edges of the emitter opening. Using plugs to define openings requires multiple processing steps and restricts the size of the openings to be plugged.
Accordingly, it is desirable to have a method of forming a bipolar transistor that can easily be scaled between large or small dimensions, that does not utilize slot processing or plug techniques, and that reduces the manufacturing costs.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. Although the devices are explained herein as certain N-channel or P-Channel devices, a person of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. For clarity of the drawings, doped regions of device structures are illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants the edges of doped regions may not be straight lines and the corners may not be precise angles.